Improved Design of a Low Power Low Noise and Frequency Stable Voltage Controlled Oscillator for Wireless Power Transfer

This paper presents a simple strategy of optimizing frequency dispersion and power consumption of CMOS ring oscillator which can be used to transmit power through the human body at 13.5 MHz and reduce the size of the implant. Three-stage ring oscillator is designed using MOS capacitor in the output of each delay cell and added resistor to improve frequency stability. A supply voltage of 1V is used in the simulation whereas the control voltage varies from 0V to 0.6V. In the simulation, 90nm CMOS process technology has been used. A linear tuning characteristic has been accomplished ranging from 12 MHz to 25 MHz in the interest of wireless applications. The circuit shows an exceptionally steady output waveform in various parameters with exceptionally low power consumption of 53.4 µW. The phase noise (-125 dBc/Hz) is pretty good taking into account the higher oscillation frequency of the circuit.