Design of Test Compression for Multiple Scan Chains Circuits

As technology advances, testing of an integrated chip is quite complex because of scaling of channel length. Testing methodologies of automatic test equipment are majorly important to test any chip at circuit level. As huge number of test patterns are used to test a circuit, test compression is critically required therefore reducing the test duration and also number of test patterns. Decompression method generates seeding for linear feedback shift register (LFSR) continually therefore skipping the LFSR lock out for limited number clock cycles. This required separate controlling for scan chain and decompressor. This paper studied effectiveness of decompression, number of parallel inputs at LFSR and also scan chains. A state skipping LFSR proposed with basic exclusive or (XOR) gates thereby number of test patterns are reduced and also delay reduced through hardware. The proposed method simulated on Xilinx 14.7 ISE and implemented on Vertx-7 FPGA as target device. The state skipping method reduces approximately 30% of test compression in terms of test cycles when compared to conventional LFSR.