An Area-Efficient High-Resolution Segmented ΣΔ-DAC for Built-In Self-Test Applications

Sigma–delta (
$\Sigma \Delta$
) digital-to-analog converters (DACs) are commonly used to realize programmable dc voltage generators in built-in self-test (BIST) schemes, largely on account of their high linearity. Unfortunately, such
$\Sigma \Delta $
-DACs require large amounts of digital memory and a reconstruction filter with a large silicon area footprint. In this article, a segmented DAC architecture is proposed. The proposed architecture is realized using two sub-DACs, where both are
$\Sigma \Delta $
-based. This DAC provides two advantages: filter footprint size reduction and memory savings, thereby allowing for a simpler BIST solution. The benefits of using the segmented
$\Sigma \Delta $
-DAC are shown using two experimental prototypes. The first is an IC prototype design using the TSMC 65-nm CMOS technology. It will be shown that the IC achieves 12 bits of resolution from 1020 memory elements, whereas an unsegmented
$\Sigma \Delta $
-DAC uses 4095 elements to obtain the same resolution. This is about a 75% savings in memory elements. The segmented prototype occupies 0.5 mm
²
of silicon area, whereas the unsegmented design occupies 0.77 mm
²
for the same resolution. A 35% silicon area savings compared with its unsegmented counterpart. A second prototype implements the segmented
$\Sigma \Delta $
-DAC architecture using discrete components. The discrete prototype achieves 16 bits of resolution from 1020 memory elements, whereas the unsegmented counterpart uses 65 535 bits for the same resolution. This is a 98% saving in memory elements.