Energy-Efficient Task Scheduling in Design of Multithread Time Predictable Real-Time Systems

The paper presents balanced heuristic techniques of static tasks scheduling in multi-core real-time system architecture. The main objective was to minimize the energy consumed by the system without causing deadlines to be missed. The authors proposed a few scheduling scenarios based on modifications of different parameters of the system and defined appropriate algorithms. The methodology was verified and tested on the original hardware platform of the system developed by the authors. The system consists of the reconfigurable set of cores based on an interleaved pipeline processing scheme. The entire system was modeled as original IP at the RTL level in VERILOG and implemented on a Virtex7 FPGA platform. The tasks were executed as a set of programs based on Mälardalen WCET benchmarks; commonly used by the PRET community for validation time predictable systems and worst-case analyses. Many series of experiments were carried out and the results validated the approach and showed that it is possible to radically reduce the energy consumed by the system while retaining timing conditions (i.e., deadlines). The authors gathered and discussed results and formulated a set of recommendations for the safety real-time system’s design flowchart aimed to minimize the energy consumed by the system.