An Effective Block Pin Assignment Approach for Block-Level Monolithic 3-D ICs

In a 2-D design, the block pins are located at the periphery of a block optimally since blocks are placed side-by-side horizontally in a single placement layer. However, monolithic 3-D (M3D) integration relieves this boundary constraint by allowing vertical block communication between different tiers based on an nm-scale pitch of 3-D interconnection. In this article, we present a design methodology named pin-in-the-area that assigns block pins at any position inside the boundary of a block using commercial 2-D place-and-route (P&R) tools and enables an efficient block implementation and integration for a block-level M3D integrated chips (ICs). Our pin-in-the-area starts from the netlist restructuring and connectivity-aware tier-by-tier chip planning, which defines blocks and decides their sizes and
$(X,Y,Z)$
locations for a two-tier M3D design. Next, we perform wirelength-driven 3-D placement to minimize 3-D half-perimeter wirelength (HPWL) and find optimal pin locations inside the boundary of a block. Once block designs are done, we apply the unique macro handling scheme to the top-level timing closure. Based on a 28-nm two-tier M3D hierarchical design result, we show that our solution offers 13.6% and 24.7% energy-delay-product reduction compared to the M3D design with pins assigned at the block boundaries and its 2-D counterpart, respectively.