Automated Testing Algorithm for the Improvement of 1T1R ReRAM Endurance

One of the most attractive types of novel nonvolatile memory concepts is resistive random access memory (ReRAM) based on a reversible (“soft”) dielectric breakdown effect. The interest is caused by combining simple architecture with promising performance: excellent scalability, nanosecond speed, long data retention, and low power consumption. However, the commercialization of this type of memory is retarded mainly due to serious drawbacks: high cell-to-cell variability of switching parameters and limited endurance related to the ionic origin of resistive switching effect coupled with the problem of voltage overshooting. In particular, these issues complicate the examination of test samples because during the lifespan of memory cells, and the permanent reselection of test switching parameters is required. This challenge can be overcome by developing a measurement technique that combines careful testing of every single structure and the ability to test a large number of test structures. As such a technique, we propose an automated testing algorithm that automatically avoids voltage overshooting and provides an effective way of characterization of cell-to-cell and cycle-to-cycle variability. It includes all stages of ReRAM cell operation, specifically electroforming, dc switching, and endurance testing in the pulsed mode. The developed technique allows on-the-fly restoring of the memory window in case of its degradation, making it possible to better understand the potential of the material stacks of the memory cell.