A Multi-Context Neural Core Design for Reconfigurable Neuromorphic Arrays

In the post Moore’s Law era, neuromorphic computing emerged as a promising solution to overcome the von Neumann bottleneck with a goal to create computing architectures that operate more like the human brain. Many neural processors have been designed in the push toward this goal, but developing a neural core architecture that is flexible enough to take advantage of both digital and analog implementations without a system-wide revision has proven to be a challenge. This paper proposes a new neural core (nCore) design that achieves this multi-context flexibility with use of a two-stage pipelined structure. The pipelined structure enables hardware sharing such that each nCore contains the functionality of multiple "virtual neurons" that save in area utilization and power consumption relative to previous neural core designs. The proposed nCore design has been implemented on a FPGA as well as an ASIC in a 65 nm CMOS process. Results are presented which show that the proposed nCore outperforms an existing digital neural core design containing a single neuron per core, DANNA2, in terms of both area and power per neuron. The improvements are made more evident with an increasing the number of functioning neurons per core.