Low Bitwidth CNN Accelerator on FPGA Using Winograd and Block Floating Point Arithmetic

Convolutional neural networks (CNNs) have achieved near or exceeding human performance in computer vision, yet their large computational and memory requirements made them difficult to deploy in both large data centers and embedded systems. CNNs are typically trained with floating point for accommodating large dynamic ranges of values during training. However, the large range of values comes with increased resource usage, power consumption, and latency. Fixed-point quantization is promising towards reducing the resource requirements of CNNs, yet low bitwidth implementations require fine-tuning to recover accuracy. In this work, we propose a CNN accelerator that utilizes block floating point (BFP) for reducing bitwidth to 10-bit and supporting Winograd filtering algorithm. We compare our design with a baseline FP16 design and show that our block floating point quantization reduces 50.1% LUTs, 48.3% Register, 27.3% BRAM and 43.8% DSP as well as achieves 32.1% higher frequency. Finally, we perform case studies with different CNNs and show that the accuracy drop is within 1% of the FP32 network.