A Linear Wideband CMOS Balun-LNA With Balanced Loads

This brief presents a novel structure on balun-LNAs which has a differential output with symmetric loads without any need for current bleeding circuit. The proposed structure is based on the common-gate (CG) common-source (CS) cascode LNA with identical transconductances for the CG and CS stages using a positive feedback for input matching compensation. This brief also introduces a new linearity improvement technique based on post distortion and derivative superposition linearization techniques without affecting the input impedance matching condition or requiring considerable power overhead. By this way, despite other linearity improvement techniques, the voltage gain not only is not decreased but is also improved. The proposed balun-LNA structure is designed in a 65 nm CMOS technology and covers the frequency range of 0.47-3.3 GHz. It has symmetrical loads with the maximum S
₂₁
of 22 dB and a minimum noise figure (NF) of 2.57 dB. The achieved third-order input intercept point (IIP3) and second-order input intercept point (IIP2) are +2.81 dBm and 29.27 dBm, respectively. The circuit consumes 8.33 mA from a nominal supply voltage of 1.5 V, and excluding the pads, it occupies 0.057 mm
²
silicon die area.