A calibration algorithm for a 16-bit multi-path pipeline ADC

Presents a calibration algorithm to design and, characterize a 16-bit analog-to-digital converter, (ADC). The main goal is to build a 16-bit multi-path pipeline ADC with a very high spurious free dynamic range, (SFDR), operating around 20 MHz. The multi-path pipeline ADC consists of 4 time-interleaved pipeline ADCs. With channel calibration using the accuracy bootstrapping technique and global calibration using normalization.