Parasitic Resistance Reduction for Aggressively Scaled Stacked Nanosheet Transistors

An analysis of NanoSheet (NS) transistor parasitic resistance components is presented and correlated to the resistance readout on Si wafers. With this model, it is possible to identify which components cause the parasitic resistance increases as CPP (contacted poly-Si pitch) further scales from 48 nm to 44 nm pitch. In this study, an alternative MOL (middle of line) metallization scheme is implemented to reduce circuit RC delay. This model helps to further reduce the transistor parasitic resistance from NFET/PFET S/D (source/drain) epitaxy or silicide. As CPP scales, NS PFET parasitic resistance reduction is more challenging and requires optimization in S/D epitaxy, silicide and metallization. Based on parasitic resistance modeling, we present a new wrap-around contact structure which eliminates the vertical epi resistance component, hence reducing overall device resistance.