Effect of the Blocking Oxide Layer With Asymmetric Taper Angles in 3-D NAND Flash Memories

The tapered channel effect is a major concern in three-dimensional (3-D) NAND technology because the effect causes differences in the electrical characteristics, including the threshold voltage (V
_T
), between the upper and the lower cells. We simulated the tapered channel effect by using Sentaurus technology, computer-aided design (TCAD) tools, and based on the results, we propose a novel method to lessen the non-uniformity of the threshold voltage shift ( ΔV
_T
) between the cells. The difference in ΔV
_T
between the upper and the lower cells due to the tapered channel can be reduced by employing a tapered blocking oxide layer with a proper taper angle. These results will be helpful in designing reliable 3-D NAND flash memories.