FPGA based timing calibration scheme for embedded EFUSE

This paper first introduces the influence of process parameter fluctuation on FPGA interconnect timing. Then, according to the characteristics of FPGA architecture and the implementation method, the reason of FPGA chip yield reduction caused by interconnect timing difference is analyzed. Finally, this paper proposes a technical scheme of embedded EFUSE timing calibration, and introduces the calibration circuit. Chip test results show that the scheme can effectively control interconnect timing deviation and improve FPGA chip yield when process fluctuation is serious.