A Low Latency Parallel Bus Interface for High-Speed multi-FPGA RT-Simulations

In this paper we present a low latency interface for high-speed multi-FPGA real time simulation. The interface developed is based on a parallel bus structure and has been implemented using two Virtex Ultrascale-plus devices. The operation of the interface is -at first- evaluated using a linear feedback shift register to compare numerical values exchanged over the bus. We then proceed providing an example of how the interface is used for the simulation of a power electronics system - composed of two dual active bridge converters- using a time step of 70 ns. The results of the decoupled simulation are verified against the one of a monolithic solution running on a single FPGA.