Electrical and Morphological Characterizations of 3-D Interconnections for Quantum Computation

Large-scale integration of quantum bits (qubits) requires 3-D architectures functional at sub-Kelvin temperatures. Electrical signals are transferred through 3-D interconnects to control and read out the information stored in the qubits. Careful design of the interconnects in terms of used materials and dimensions is, thus, essential to optimize the whole system performance. To help the design of future quantum architectures, we benchmark two interconnect technologies based on SnAg microbumps and Cu/SiO
₂
hybrid bonding. We report electrical and morphological characterizations performed on 20-
$\mu \text{m}$
pitch daisy chains (DCs) fabricated with die-to-wafer processes developed at CEA-LETI on 300-mm Si wafers. DCs with more than 20 000 SnAg microbump-based interconnects and more than 1000 direct Cu-bonded ones have been electrically characterized in a He
³
cryostat between 300 K and 500 mK. These measurements allow extracting unitary link resistances, establishing a preliminary process design kit at these low temperatures. The lack of defects and cracks on cross section electron micrographs performed after the low-temperature electrical measurements confirmed the mechanical robustness of these interconnect technologies to thermal variations between the room and sub-Kelvin temperatures.