A Reference-Waveform Oversampling Technique in a Fractional-N ADPLL

This article presents a low-power fractional-
${N}$
all-digital phase-locked loop (ADPLL) employing a reference-waveform oversampling (ROS) phase detector (PD) that increases its effective rate four times, thus leading to lower jitter and settling time. The proposed ROS-PD adopts a bottom-plate sampling with a voltage zero-forcing technique, which yields high power efficiency and supports fractional phase compensation in the voltage domain through a programmable DAC. The PD output is then amplified by a low-noise gated amplifier and digitized by a low-power successive approximation register analog-to-digital converter (SAR-ADC). Leveraging the benefits of digital architecture, gain mismatches from the waveform estimator are calibrated by means of an LMS algorithm, consequently lowering fractional spurs. The proposed ADPLL is implemented in TSMC 28-nm LP CMOS. The prototype generates a 2.0–2.3-GHz carrier with an rms jitter of 414 fs while consuming only 1.15 mW. This corresponds to a state-of-the-art ADPLL FoM
_jitter
of −247 dB in a fractional-
${N}$
mode. Due to the wide (largely linear) monotonic range and
$4\times $
oversampling rate from a 48-MHz reference, without any additional circuitry, the proposed ADPLL can settle within
$3~\mu \text{s}$
in face of a 70-MHz frequency step.