Implementation of 4×4 2D Mesh NoC Architecture using FPGA

The network-on-chip (NoC) approach arose from several factors that led to the emergence of this technology in the electronics industry and to replace the problematic classic interconnections. NoC is an approach to design the communication between intellectual property (IP) cores in a system-on-chip (SoC). In this paper, a 2-dimensional mesh network is implemented with a 4×4 node matrix. The node consists of a network interface (NI), IP, and router. A common switch in NoC is the router which is responsible for packet switching from input buffers to the output buffers according to the routing protocol algorithm. The router has five ports (north, right, east, west, and local) to receive/ direct the packets from/ to the appropriate port. The proposed router in this work was designed with two additional array buffers for storing packets to avoid congestion when multiple packets transmit from the same output port, which creates competition. The XY routing algorithm was mainly adopted to identify the path taken by a packet between the source and destination. The system design was programmed using the Very High Speed Hardware Description Language (VHDL) and then simulated using the software package ISE 14.6. The design was validated through simulation and experimentation based on Spartan 3AN (xc3s700AN). The results proved that the system's architecture is effective in terms of packet-passing, especially with the addition of the two array buffers for the routers, low latency particularly between the adjacent routers, and low resources.