FPGA-based Multi-Phase Shift-Clock Fast-Counter Time-to-Digital Converter for Extremely-Large Number of Channels

In nuclear physics time-resolved experiments, the improvement in temporal resolution of detectors from nanoseconds to hundreds of picoseconds, and the increasing of the number of channels required in the applications move the research through the design of Time-to-Digital Converter addressable to programmable logic device, i.e. Field-Programmable Gate Array(FPGA) and System-on-Chip (SoC). In this contribution, we present the implementation strategy of a resource-saving, multi-phase Shift-Clock Fast-Counter (SCFC) Time-to-Digital Converter (TDC) designed to be implemented on FPGA. The SCFC-TDC has been designed to guarantee hundreds of picoseconds resolution over a microseconds full-scalerange (FSR) with hundreds of channels. In order to reach high-resolution over a so extended FSR Nutt-Interpolation is used, i.e.merging a coarse with a fine component of the measure. The coarse part is obtained by sampling counter at maximum 400MHz, whereas the fine part is obtained simply reading the phase of shifted clocks, generated by a Phase-Locked Loop (PLL). The kernel of the SCFC is made by T flip-flops used to obtain simple 1-bit counters that work in synergy to produce the fine part ofthe measure. The advantage of the SCFC-TDC with respect to a Tapped Delay-Line one, is the low area consumption, which hundredsof channels implemented in the same FPGA. Furthermore, the proposed SCFC architecture is not based on delayed datasampling method, so it is completely synchronous. This avoids the use of the constraint file set in placing critical parts of the firmware. We have designed the SCFC-TDC as an IP-Core compatible to the last generation of 28-nm Xilinx 7-Series FPGAs and SoCs. Furthermore, we have tested the proposed solution in two economic and compact FPGA targets: the Artix 200T and 35T. We have achieved a resolution up to 156.25 ps, using only 249LUT and 440 FF per channel. This guarantees to have almost100 channels on a single device.