A 24-Channel Digitizer and Digital Serial Interface ASIC for High-Speed Detector Instrumentation

A 24-channel application specific integrated circuit (ASIC) intended for the readout of high-speed particle detectors is presented. The chip comprises 24 preamplifiers, 24 12-bit, 25 MS/s Pipelined Analog-to-Digital Converters (ADCs) with self-calibration, an internal PLL, and a 3 Gbps serial interface that conforms to the JESD204B standard. To simplify interfacing with a variety of sensors, the ASIC also includes an automatic offset calibration loop. The high-level of integration of the ASIC reduces overall system cost and area, and exploiting the signal characteristics of the typical sensors allows the ADC to be optimized for reduced power dissipation. The use of an integrated serializer and an industry standard protocol simplifies integration of the ASIC into a complete detector system. An ASIC illustrating the concept, called the High-Speed Image Preprocessor Targeted for Electron Readout, or HIPSTER, with a die area of 64.26 mm
²
, is packaged in a 480-ball BGA, and is fabricated in a 180 nm CMOS technology. HIPSTER includes a front end matched to the sensor and achieves typical DNL <; 0.55 LSB, input-referred thermal noise of 114.5 μV-rms, and a BER of better than 10
^-14
. The power dissipation is 98 mW / channel.