A Low-power ASIC with Row-column Summing Structure for 64-channel SiPM Readout

FESA is an analog application-specific integrated circuit (ASIC) to read out timing and energy signals from 64-channel silicon photomultiplier (SiPM) arrays. The fast preamplifiers for each channel are regulated common-gate (RC-G) TIAs that are optimized to consume less power consumption meanwhile maintaining a low input impedance and high bandwidth. The 64 timing signals are summed together inside of the chip as one output signal which indicates the arrival time of events. By the row-sum and column-sum readout structure, the 64 energy channels are compressed into 16 energy signals. Instead of using high-speed analog-to-digital converters (ADCs) for energy measurement, the amplitudes of the energy signals are translated into time widths by 16 linear-discharge time-over-threshold (TOT) conversion modules, which are then digitized by off-chip 16 channels of time-to-digital converters (TDCs). Such arrangements can simplify the ASIC design and reduces its power consumption largely. FESA was taped out with GF 0.18 µm CMOS technology and its performance evaluation setup was constructed. Using a PET detector, which consists of a SiPM array (KETEK PA3325) coupled with an 8×8 LYSO crystal array (3.12×3.12×10 mm
³
for each crystal), and a coincidence detector (PMT R9800 coupled with LaBr3 crystal), the coincidence time resolution (CTR) was measured as 422.3 ps, and the energy resolution for
²²
Na radiation source was measured better than 12%. The measured flood image of the detector also proves that FESA has the potential to achieve a good spatial resolution for pixelated PET detectors.