Ripple Suppression in Capacitive-Gain Chopper Instrumentation Amplifier Using Amplifier Slicing

This paper proposes a power-up calibration scheme to mitigate the offset of a capacitive-gain chopper instrumentation amplifier (CCIA), thus suppressing the offset-induced output ripple. In this design, the first stage of the error amplifier is formed by multiple identical slices. Before normal operation, the offset polarity of each slice is determined by reusing the second stage of the amplifier as a comparator. With such polarity information, slices of the first stage are regrouped to achieve a statistical offset reduction. The proposed amplifier has been fabricated in a standard
$0.18~\mu \text{m}$
CMOS process with an area of 0.57 mm
²
, achieving an average peak-to-peak output ripple of 58 mV. The amplifier consumes
$1.53~\mu \text{W}$
with a 1.2 V supply. Compared to the state-of-the-art, the calibration time of the proposed scheme is much shorter (14 clock cycles) and the overhead logic consumes no static power after calibration. In addition, the slicing technique provides an extra degree of freedom to the amplifier for bandwidth and noise scaling.