Backside cavities for thermal tuning optimization of silicon ring resonators

Silicon ring resonators on SOI substrates are well known and widely studied devices for silicon photonics-based systems. They are commonly used in datacom and highperformance computing for wavelength multiplexing, modulation and spectral filters. They can be tuned to the desired frequency with resistive heaters, which is the primary power budget of the device. In this work, backside cavities have been successfully etched in the bulk of the SOI substrate below ring resonators to improve heat trapping within the silicon rings. Simulations show that those backside cavities improve significantly heat confinement and minimizes locally heat losses due to conduction in the Si substrate. All the processes used in this study are compatible with the standard silicon photonics interposer process flow. A 72% power consumption reduction for a 10 μm diameter ring resonator on SOI has been achieved with a backside opening of 100 μm deep and 40 μm diameter, in good agreement with simulation results. Most importantly, the cavities opening did not impact the optical performances of the ring. Dynamic behavior of the rings was also studied, and show that the presence of cavities increases the thermal switching time of the rings.