Reliability Considerations for Wafer Scale Systems

With the ever-increasing complexity of wafer scale systems as well as higher computing power requirement, reliability of these systems have become a major point of concern. The wide range of organic and inorganic materials used results in large CTE mismatch and ultimately high thermomechanical stresses. Moreover, failure due to moisture ingress in harsh environments and challenges of developing novel encapsulations with high step coverage, high throughput and robust barrier properties is another issue that is receiving a lot of emphasis. To improve the performance of the wafer scale systems, we have developed silicon interconnect fabric (Si-IF) which is a heterogeneous integration platform that utilizes metal-metal thermocompression boding to integrate dielets on a Si wafer as substrate. We have shown the advantages of Si-IF compared to conventional platforms in terms of performance, power consumption and heat dissipation [2], [3]. Replacing solder joints with metal-metal joints and limited number of materials used in Si-IF, result in low thermomechanical stresses and elimination of intermetallic compound formation during operation and fabrication and thus, improving the reliability and lifetime of the system. Currently, we are developing a sophisticated wafer scale system where Si-IF is at the heart of the platform and is connected to a two-phase thermal management unit and power platform, moreover flexible connectors are used to make the connection between Si-IF and the outside world. In this wafer scale system, solder joints are used to make connections between Si-IF and power platform as well as flexible connectors, thus it is important to investigate stresses within the joints due to temperature variation and vibration. In this paper, we investigate use of elastomer buffer layer as stress relaxer to improve the reliability of this large wafer scale system. Finite element analysis (FEA) modeling was utilized to understand the change in the thermomechanical stresses arising during temperature cycling for a system with the buffer layer when compared to a system with no buffer layer as well as a system where PCB pieces are embedded in the buffer layer. We present the simulation results for temperature cycling of the Si-IF attached to a substrate for all three scenarios. Temperature was varied between 125°C and −40°C and the maximum Von Mises stresses in the solder joints were extracted. FEA results show that maximum stress level is significantly lower when an elastomer layer is used as a buffer layer and embedding the PCB pieces in the buffer layer further reduces the stress levels. Moreover, we investigated use of elastomer buffer layer as stress relaxer to improve the reliability of this large wafer scale systems. FEA simulations show the effectiveness of an elastomeric buffer layer in damping the random vibration. The analysis shows that addition of the elastomer to the system effectively damps the input random acceleration and consequently, reduces the stresses that the solder joints experience and improves the lifetime of the system.