Exploring Carrier Transport Mechanisms of Inversion, Accumulation, and Junctionless Mode of Vertical Stacked Nanosheet Field Effect Transistor for N5 Logic Technology

Inversion Mode (IM), Accumulation Mode (AC), and Junctionless Mode (JL) of Nanosheet (NS) Field Effect Transistor (FET) are explored for potential sub 5-nm logic technology node (N5) using 3D TCAD simulation. The devices are simulated with gate lengths (LG) of 12 nm, EOT 0.8 nm, and three vertical stacked channels. For IM and AC NSFET, the electrons are distributed in the center. The effects of surface geometry-dependent current density combined with quantum confinement effect make a bow tie-shaped electron distribution. In the other hand, the carriers of JL NSFET are also concentrated in the center of NS channel layers and forms partial depletion. These JL mechanisms can give benefit less sensitive to surface roughness interface between oxide and channel. It is also observed that the depletion width would increase as the gate voltage increases, thus decreasing the depletion and total capacitance. These characteristics indicate that the JL NSFET with less capacitance can become alternative promising logic devices for enhancing the device performances.