Signal and Power Integrity Analysis of A 0.38 pJ/bit 12.8 Gb/s Parallel Interface for Die-to-Die Link Applications

MediaTek link GEN II (Mlink2.0), the worldwide first successful heterogeneous Die-to-Die communication IP with the operating speed of 12.8 Gbps and the power efficiency of 0.38 pJ/bit has been in mass production on high data bandwidth SoC applications. In order to sustain internal ISI, crosstalk, and SSO noise, and reflection effect on the non-termination scheme for low-power and high-speed designs, optimizing matching networks and constructing shielding guards to against these interference were the major signaling design challenges. In addition, considering benefits from clean power source for jitter performance, an embedded capless LDO design was adopted for critical clock path as well. In this paper, a systematic approach to design data path in a limited beachfront with
$\mu \text{Bump}$
pitch
$\mathrm{48}\ \mu \mathrm{m}$
condition is proposed. In first part of paper, several I/O circuit versus InFO channel design considerations are discussed such as shielding structure, mode impedance control, driving strength ability and RX termination scheme. In the second part, signal integrity design flow of ultra-short- reach (USR) and topology of interconnects are discussed. Finally, given fully consideration on system power rail network and local InFO SI/PI configuration, the timing budget of Mlink2.0 design has achieved over 70% pass windows in both co-simulation and silicon shmoo verification. The compatible interposer design at InFO and CoWoS will be discussed for wider system applications and design flexibility in the future.