Investigation of a Novel Substrate Core Material Designed to Reduce Package Warpage and Improve Assembly-Level Reliability

Rapid advancements in IoT and AI technologies, are driving ever more sophisticated and powerful LSI chip designs. These semiconductors are used in a broad array of end-use applications and industries including Automotive (under-hood, sensors and infotainment), Network Devices, Servers, PCs, AI Processors, Gaming Consoles and the like. Increasingly, these LSI chips are mounted in FC-BGA packages. This deployment trend is powering the development and adoption of a variety of FC-BGA packaging structures like Large-Chip, Multi-Chip and 2.5D packaging schemes. The advancements in chip processing power and functionality are driving an increase in I/O counts, which, in turn, is compelling a corresponding increase in the size of the IC substrate. However, as package dimensions increase, package warpage also increases. Warpage is primarily the result of the strain produced by the CTE mismatch between the silicon chip and the organic substrate. When the warpage becomes too extreme, chip mounting defects may result. One generally accepted solution is to employ a lower CTE core material to reduce the substrate-core CTE mismatch and increase the reliability of the chip mounting process. While the warpage of the package structure maybe be reduced with a lower CTE substrate, employing this approach alone tends to push reliability issues downstream: it effectively increases the CTE mismatch between the package substrate and the mother board resulting in an increase in surface mount assembly defects. Traditionally, IC packagers face a design trade-off between the warpage of substrate and the reliability of the second level mounting. This is a serious impediment for the evolution and adoption of FC-BGA technology. While assembly level polymer reinforcements like underfills and sidefills may be used as a countermeasure, these materials add considerable cost and complexity to the manufacturing process. In this research, a new substrate core material was designed to overcome the trade-off between the warpage of the package substrate and assembly-level reliability. This material combines ultra-low CTE performance with a unique stress release resin technology. This paper describes the modeling, development and testing of the novel core material. First, the substrate material warpage targets were determined with simulation software. The results indicated that the new core material should have a lower CTE value than the control (a conventional core material). Based on these targets, experimental IC substrates were fabricated, and their warpage was measured. The results correlated with the material simulation; the substrates made with the new core material exhibited less warpage than the control. Second, the reliability of second level assemblies made with the different cores were modelled. This new material exhibited the unique characteristic of extremely high elongation compared to conventional core materials. It was hypothesized that this elongation characteristic would significantly decrease the stress on the solder balls between the substrate and the mother board, and this reduced stress on the board-level interconnects would increase the assembled reliability. Board-level reliability testing confirmed the simulation results and demonstrated that packages made with new core material performed better than those made with the control. This study concludes that the hypothesis was correct; FC-BGA substrates made with a core combining ultra-low CTE properties with a unique stress release technology exhibit lower warpage and increased board-level reliability than conventional core materials. These results demonstrate that the traditional trade-off between substrate warpage and package level reliability can be overcome with this novel and new core material technology.