Novel high-power delivery architecture for heterogeneous Integration systems

Moore's law of transistor scaling over the past few decades warrant a paradigm shift in packaging and integration methodologies. Silicon interconnect fabric (Si-IF) technology is a wafer-scale, fine pitch, package less, heterogeneous integration platform that enables high package density by supporting dielet assembly at fine spacing. In Si-IF technology, bare dielets are assembled on a prewired silicon wafer using thermal compression bonding (TCB) at a small inter-dielet spacing (\leqslant 100 μm) using fine pitch die-wafer interconnects (\leqslant 10 μm). This enables Si-IF technology to support high power systems on a wafer. A novel high-power delivery architecture enabling 40-60 kW power delivery to a 300 mm wafer is outlined. Prototype results for power delivery are presented.