Advanced Gate Stack Design of Ferroelectric Transistor for Scaling towards 7nm FinFET Platform

Ferroelectric-metal FinFET (FeM-FinFET) has been proposed and verified by TCAD simulation. Compared to the ferroelectric FinFET (Fe-FinFET), FeM-FinFET could achieve the logic compatible program/erase voltages (less than ±1.5V) owing to the enhanced electric field on the ferroelectric layer by the area ratio between the ferroelectric capacitor and the oxide capacitor. In addition, the position of the ferroelectric capacitor helps the FeM-FinFET to sustain the scalability towards 7nm.