Geometrical Optimization of 10 nm Channeled TG–HOI FinFET using tri-layered Strained Silicon Channel

With continuous scaling of MOSFETs dimensions, the efficiency of the MOSFET devices have deteriorated. Beyond 20 nm, scaling becomes even more challenging as FinFETs are also prone to short channel effects. So different technologies are the need of the hour to replace the existing materials and determining ways of enhancing the on currents. One of these methods is the employment of strained silicon technology. In this paper, multiple 3D Trigate FinFETs having 10 nm channel length are developed with different dimensions of tri-layered strained silicon channel, encompassing two silicon layers with a ${\mathrm {Si_{0.6}Ge_{0.4}}}$ layer sandwiched in between. The electrical properties of all the devices are characterized to arrive at an optimized geometrical dimension of the tri-layered strained silicon channel thereupon reducing chip area.