FPGA implementation of a QRD-RLS-based equalizer for MIMO systems

In this work, we propose an FPGA implementation of an eight analog-channels equalizer based on the QR Decomposition - Recursive Least Squares (QRD-RLS) algorithm for MIMO systems. In order to reduce the complexity, we developed a very efficient architecture where the compensation of the amplitude and phase distortions, introduced by the analog channels, is achieved by means of a single QRD-RLS cell. This cell is properly shared over time on the eight channels present. This solution is possible considering the slow variations of the quasi-stationary real channel. Taking advantage of the above considerations, in this paper we propose a very efficient implementation of the QRD-RLS algorithm, which requires very little hardware resources. The proposed system has been tested and validated through the FPGA-In-The-Loop method. Results show that the proposed system provides a magnitude ripple less than 0.005 dB and a group delay ripple less than 0.4 ns that meet the constraints of the actual application.