A 1.1-V 10-Bit 25-MS/s 7.58fJ/conversion-step SAR ADC in 40-nm CMOS

A low-power 10-bit 25-MS/s asynchronous successive approximation register analog-to-digital converter (SAR ADC) is proposed in this paper. The lower side-set (LSS) switching scheme is proposed, which consumes zero switching energy for the two most-significant bits and saves 75% of the capacitor area compared to the traditional switching scheme. The two-stage dynamic-latch comparator is applied to complete the high-speed operation without high current consumption. The use of asynchronous controller reduces the harshness of the comparator's high-frequency clock. In order to optimize the power consumption of SAR logic circuit, a dynamic logic unit is employed. The prototype 10-bit SAR ADC is designed in a 40-nm CMOS technology, showing a SNDR/SFDR of 53 dB/76.95 dB at 11 MHz input, under a 1.1-V power supply, while consuming 68.64 µW at 25 MS/s for a figure-of-merit of 7.58 fJ/conversion-step.