JPEG Image Compression Using Multiple Core Strategy in FPGA achieving High Peak Signal to Noise Ratios

Field Programmable Gate Arrays are increasingly becoming an integral part of modern embedded system designs because of their ease of implementation, flexibility and unparalleled processing power capability. Taking into consideration these capabilities, a compression algorithm has been implemented on an FPGA (Xilinx Spartan 3A 3400 Kit) while the decompression part has been carried out on a Personal Computer (PC). The transmission between FPGA and PC has been done through Ethernet interfacing. Decompressor has been designed in MATLAB to decompress the data acquired through FPGA while the compression algorithm used is based on JPEG. Three different images have been considered for the test case purposes. Likewise, three resolutions of each image have been used for compression in FPGA and subsequent decompression using MATLAB in PC. Multiple cores strategy has been incorporated in the FPGA to speed up the compression process. The pictorial representation of each decompressed image viz-a-viz original image has been carried out. The Peak Signal to Noise Ratio (PSNR) and Mean Square Error (MSE) have been calculated for each set of resolution for comparing image compression quality. The graphical representation of Mean square Error for all resolutions of each image separately has been depicted.