PATARA: A REVERSI-Based Open-Source Tool for Post-Silicon Validation of Processor Cores

This paper presents an open-source tool, called PATARA, for post-silicon validation of Application-Specific Instruction set Processors (ASIP). PATARA is based on the REVERSI approach, which can significantly speed up the validation time of already fabricated chip designs. It enables the generation of automatic, randomized test-benches, which are then validated by the processor itself. PARATA extends the REVERSI approach by supporting subword parallalism (i.e., microSIMD hardware mechanism), multiple issue slots, and conditional execution. The configuration of PATARA is provided by XML files, which describe the instruction set architecture (ISA) of the target custom processor. Moreover, the modular structure of the PATARA tool enables the insertion of future features. The potential of this tool is shown in a case study, where part of the instruction set architecture of a VLIW-SIMD processor, called KAVUAKA, is verified. The results show that the use of the PATARA tool can achieve a higher code coverage than the previously used hand-written testbenches. It is worth mentioning that a high code coverage in pre-silicon verification generally implies a high coverage in post-silicon validation.