A 2mW, 60GHz Mixer First I/Q Receiver in 28nm CMOS

This work presents a 60GHz ultra-low power and low noise mixer-first I/Q receiver front-end in 28nm CMOS process. The receiver consists of symmetrical I and Q stages, a quadrature hybrid providing the 90° phase shift between the I and Q signals, and differential outputs at baseband followed by a differential to single-ended baseband amplifier. Each I and Q stage is composed of differential mixer biased at subthreshold for low DC power consumption. The receiver architecture is targeted for low LO to RF leakage and low LO drive. Simulation results show a minimum single-sideband noise figure (NF) of 5.7dB with power consumption of 2mW from 1.1V supply, conversion Gain of 29.3dB, RF bandwidth of 6GHz. The IF supports 2GHz channel bandwidth with LO power drive of -7dbm and LO-to-RF leakage lower than -60dBm. The receiver size is 0.22•0.23mm
²
. The proposed I/Q receiver can serve for ultra-low power and low noise mmW phased array systems for 5G communication systems.