Impact of the Bitcell Topology on the Multiple-Cell Upsets Observed in VLSI Nanoscale SRAMs

This article presents an analysis of the multiple events [and more specifically, multiple-cell upsets (MCUs)] that may occur at successive generations of bulk CMOS static random access memories (SRAMs) operating under harsh conditions, such as in avionics or space. Such MCU distribution is greatly impacted by the bitcell topology, which, in the International Technology Roadmap for Semiconductors (ITRS)/International Roadmap for Devices and Systems (IRDS) history, experienced a drastic change in the transition between the 90- and 65-nm nodes. Experimental results obtained from proton and neutron accelerators, along with predictions issued from the MUSCA-SEP3 modeling tool, are provided. Various commercial-off-the-shelf (COTS) SRAMs manufactured by Infineon in bulk CMOS 130-nm nodes down to the 65-nm one were used as targets for the experimental results. Finally, MUSCA-SEP3 was also used to analyze and discuss scaling trends on more modern nodes (45 down to 14 nm).