A 3.3-4.5GHz Fractional-N Sampling PLL with A Merged Constant Slope DTC and Sampling PD in 40nm CMOS

In this work, we present a novel fractional-N sampling PLL architecture where the functions of a constant slope digital-to-time converter (CS-DTC) and a sampling phase detector (SPD) are merged into one block. This simplifies the PLL's critical phase detection path, saves power, reduces noise sources and improves the overall linearity. The 3.3-4.5GHz PLL implemented in 40nm CMOS achieves a 292fs rms jitter, integrated from 10kHz to 10MHz while consuming 2.4mW, leading to a PLL FoM of - 246.9dB. The in-band fractional spur is −54dBc and the PLL occupies a core area of 0.36mm
²
.