A Noise-Cancelling Self-Interference Canceller with +7 dBm Self-Interference Power Handling in 0.18μ m CMOS

Self-interference (SI) mitigation is critical for full-duplex and frequency-domain duplex systems. Canceller noise and linearity limits the SI power that can be tolerated at RX input. A dual-path SI cancellation scheme is presented where the noise and distortion from the canceller are addressed through a differential noise-cancelling path. The proposed scheme relaxes the noise/linearity trade-offs in canceller design and a 400 MHz implementation in $0.18\mu \mathrm{m}$ CMOS demonstrates 20 dB SI cancellation over 50 MHz bandwidth and 23 dB cancellation for +1dBm peak SI power while degrading RX NF by 3.8 dB.