Design, Implementation and Performance Comparison of D- Latch Using Different Topologies

This article provides the comparison results of the D-latch circuit in three different topologies i.e. conventional CMOS (Complementary Metal Oxide Semiconductor), MCML (MOS Current Mode Logic), and BD-MCML (Bulk Driven-MOS Current Mode Logic). In the BD-MCML circuit, the bulk terminal is also used as one of the inputs. The voltage levels of input should not affect the operation of the MOSFET. In BD-MCML, the dynamic power is independent of frequency, So it can be used in high frequency applications with less power consumption. The comparison is made by considering the supply voltage for all the circuits to be 0.8 V. The performance of D- Latch with different topologies is evaluated and analyzed using Cadence Virtuoso tool in 45nm technology. In this paper, the performance analysis and comparison is done using three different parameters; power, delay, and PDP (Power Delay Product). This paper concludes that BD-MCML has better performance with respect to power and PDP as compared to the other topologies,