ASIC Design of a 32-bit Low Power RISC-V based System Core for Medical Applications

The electronic devices play a decisive role in the realm of medical applications. The analysis of medical images and axial tomography scanners are uses high performance processors. There is plenty of micro-controller intellectual property (IP) available for the development of ASICs, however these are tied to restrictive, expensive licenses and typically not reliable and open for customization. The reliability being a primary concern the RISC-V core aiming to development of a scalable open instruction set architecture (ISA) for medical applications. In this paper designed and implemented the 32-bit low power RISC-V based system core from RTL to GDSII. The functional verification of 32-bit five stage RISC- V system core is caried out in NC Launch tool and generated the gate level netlist using 180nm technology library file in the Genus tool. The static timing analysis is caried out for setup and hold timing analysis in the Cadence Tempus Timing Signoff tool. The floor planning, placement and routing of 32-bit RISC- V processor is implemented on Innovus tool. The area, power and timing reports are generated at each stage in the physical design. After carrying out pre-clock tree synthesis, post clock tree synthesis and post routing of circuit, obtained the optimized results for arrival timing 9.868ps, power is 3.793mW and area is 72409.1 μm².