An Intensive Study of Thermal Effects in High Speed Low Power CMOS Dynamic Comparators

This research work intensively studied the impact of thermal effects on the logic performance of dynamic comparators implemented using 16 nm strained silicon/metal gate/high-K CMOS technology and with a power supply (V
DD
) of 0.7 V. The double tail latch type and pre-amplifier and latch type dynamic CMOS comparators exhibited a delay of 45.03 pS and 63.09 pS respectively. Moreover, the double tail latch type and pre-amplifier and latch type comparators consumed a power of 69.16 µW and 58.76 µW respectively. In order to investigate the thermal effects in dynamic CMOS comparators the operating temperature is varied from 30°C to 110°C and the pre-amplifier and regenerative latch type dynamic comparator is found to be exhibiting minimal noise compared with traditional double tail comparators. These two dynamic comparators implemented using 16 nm CMOS technology with a V
DD
of 0.7 V are considered to be promising circuits for future ultra low power and high speed ADCs.