Beyond Stability and Performance Limits in Digital Current Mode Control using Event-Based Sampling

In fixed-frequency fully digital and mixed-signal current mode control (CMC) architectures, a uniform sampling clock remains a default choice in synchronism with the switching clock. This paper shows that this results in a much restricted stability boundary in digital CMC. This requires an overcompensated emulated ramp for stability, which results in a limited closed-loop bandwidth. Thereafter, an event-based sampling method is proposed, which offers unusual perspectives and order of magnitude stability improvement with superior dynamic performance over uniform sampling in digital CMC. Current loop stability analysis and small-signal design are presented. An identical emulated slope in digital CMC can achieve stability and performance similar to mixed-signal and analog CMC. The proposed sampling method further improves performance and stability in MCMC and allows designers to apply large-signal control and tuning in digital CMC to achieve near time optimal performance. Performance improvement using the proposed method is demonstrated analytically and through simulation using a synchronous buck converter.