Sampling Delay Effect on Stability in a Multi-Phase Buck Converter using Digital Current Mode Control

Fixed-frequency digital current mode control (CMC) architectures find widespread applications in low-voltage-high-current multi-phase DC-DC converters for fast transient performance using high bandwidth controllers. Using an experimental case study, this paper shows that a closed-loop multi-phase buck converter using mixed-signal CMC (MCMC) exhibits sub-harmonic instability even when individual analog current loops are stable for low duty ratio operations, and the nature of instability is somewhat different from analog CMC. This results in poor phase current balancing, higher RMS current and voltage ripple, thereby leading to higher conduction losses with poor voltage regulation. Unfortunately, analytical results are not readily available to address such instability problems in a digitally CMC multi-phase DC-DC converter. This paper develops a discrete-time modeling framework and shows that a sampling delay can completely change the stability status of a two-phase buck converter governed by both MCMC and fully digital CMC (DCMC). Further, dynamic ramp compensation methods are proposed for enhanced stability with high performance.