A 670-GHz 4 × 2 Oscillator–Radiator Array Achieving 7.4-dBm EIRP in 40-nm CMOS

A 670-GHz terahertz source array is implemented in 40-nm bulk CMOS technology. To increase the frequency and power of the source, a compact and 1-D scalable oscillator–radiator topology that works on the third harmonic is proposed. In order to avoid the gate transistor node from loading the tank at the output frequency, a filtering feedback network is used to feed through the fundamental signal while filtering the third harmonic. The source consists of
$4\times 2$
oscillator cells with different common- and differential-mode coupling mechanisms that are built into the slotline resonant tanks. These slotlines build up an
$E$
-field pattern that radiates the signal to the far-field. The chip is assembled on a hyperhemispherical lens that suppresses substrate modes and further increases the directivity of the source. The full array and pads have a die size of
$0.75\times 1$
.15 mm
²
. The source can be tuned in the range of 660.8–676.6 GHz. It has a maximum measured EIRP of 7.4 dBm and −16.1 dBm radiated output power while consuming only 99.7 mW. The source also has a measured phase noise at 1- and 10-MHz offsets of −69 and −93 dBc/Hz, respectively.