Extraction of Undetectable Faults in 6T- SRAM Cell

As the need to store more information, the density of Static Random-Access Memory (SRAM) increases, and it occupies more space on System on Chip (SOC), hence it has become more important to test the memory. Many faults occur during the manufacturing time, the existing methods does not cover all the faults. A new fault model taking parasitic effects into consideration, to detect the faults along with fault location. In this method we consider the node-to-node open defects at the circuit level using 120nm technology. Test results observed with few existing faults like Transition Faults (TF), Incorrect Read Faults (IRF) and No Access Faults (NAF). In addition to these, using proposed parasitic extraction method few more faults in the name of undetectable faults (UDFs) also observed, in which parasitic R & C values are varied at defect-imposed node. In this paper we observed total seven UDFs, and few are mentioned here such as UDF1 observed between transistor M1 drain and node Q with observed R value of 3.7 kΩ and C value of 4.7fF. Similarly, UDF2 located at drain of M2 drain and node Q with corresponding R value of 4.14kΩ and C value of 5.1fF