Efficiency and Power Density Optimization of Three-Level TP PFC

Si based three-level (3L) totem-pole (TP) Power Factor Correction (PFC) topology is a low cost alternative to two-level TP PFC with wide-band gap devices providing high power density and high efficiency. This study proposes a system level optimization algorithm through modeling all sub-systems of the converter including differential mode noise filter, PFC inductor, heatsink required by the FETs. Depending on the weights assigned between volume, cost and power loss, the algorithm chooses the switching frequency, designs the PFC inductor, and chooses the FETs from the database that minimizes the given cost function. In this study, a 3.7 kW 3L TP PFC is designed with a final cost function having 60%, 20% and 20% weighting coefficients for volume, cost and power loss, respectively. Results show that optimum design reached 99.01% of efficiency, with total volume of 340 cm(exp 3) for DM filter, PFC inductor, heatsink and bus capacitor.