Faster Switching with Less Overvoltage - Limitations in Current, Parasitics and Paralleled Chips

This paper explores the turn-off switching behavior of a 3rd. Gen. SiC-MOSFET at its maximum speed; that is, with zero external gate resistance. It is observed that the waveforms do not follow the typical trajectories and the device shows a mechanism that reduces the switching losses and the expected over-voltage. The behavior of a single chip is studied with the double pulse test, where the applicable area of this behavior is evaluated. The influence of chip parameter dispersion is analyzed as well as the influence of gate loop and DC-link parasitic inductance. Finally, the challenges of parallel switching are identified in simulation.