Reduction of Parasitic Inductance and Thermal Management in a Multichip SiC Half-Bridge Module

The advantages of using silicon carbide (SiC) devices can only be utilized if they are properly packaged. Existing packaging technology is based on silicon (Si) packaging technology. However, SiC semiconductor devices are much more sensitive to the stray inductance present in the module layout due to their considerably faster dynamics. This can lead to high overvoltages and oscillations during high dI/dt switching. In this paper, modifications to the inner structure of an existing SiC multichip module are proposed, while keeping the outer dimensions fixed. A detailed circuit model of the module is created by using parasitics extracted from ANSYS Q3D Extractor. This model is simulated in LTspice and compared with experimental switching waveforms of the commercial module to confirm the improved characteristics. Furthermore, increased thickness of the baseplate is investigated in terms of thermal and switching performance.