Work in Progress: Path-based Graph Partition for Parallel Hardware-accelerated Functional Verification

Functional verification of large scale circuit design is a basic problem in Very Large Scale Integrated (VLSI) design. With the increasing scale of the circuit, it is urgent to divide the whole large scale circuit into some smaller sub-circuits so as to perform parallel functional verification on multiple hardware processors. The partition problem of hardware-accelerated functional verification can be regarded as a graph partition problem. However, unlike the traditional graph partition requirements for minimum cutting, the hardware-accelerated functional verification partition needs to reduce the simulation depth and improve the parallelism of the simulation. Therefore, partition for hardware-accelerated functional verification is a problem combined with graph partitioning and schedule. While the traditional schedule algorithms have high complexity and cannot handle large scale Directied Acyclic Graph (DAG) scheduling. To tackle the parallelism, depth, and cut edge problem, we design a new method, called path-metis. Path-metis combines the scheduling idea, such as the critical path information and task priority of the DAG, into the traditional multilevel partitioning method. Our preliminary experiments on real circuits show the effectiveness of the method, and the simulation depth can be reduced by about 11.35% on average compared with metis only with 27.58% cut size increasing.