Efficiency of Parallelization of Haar Fast Transform Algorithm in Dual-Core Digital Signal Processors

The use of multi-core processors in digital signal processors, as well as universal processors, helps to increase work efficiency more than single-core processors. As a result of the development of technical means, there is a growing demand for software tools for parallel computing of signals based on multi-processor and multi-core processors. This article is devoted to evaluating the effectiveness of the parallelization of fast Haar transform algorithm, which is widely used in digital signal processing based on Blackfin ADSP-BF561 dual-core processors from Analog Devices, Inc. Functional descriptions of the ADSP-BF561 dual-core processor architecture are given. The parallel algorithm has been developed for the fast transformation of Haar on Andrews. The creation of a parallel computing program for dual-core processors on the VisiualDSP++ development environment is considered. The application project describes the structure of the interconnection of the cores in the use of common data. The results of the time spent calculating fast Haar transform based on the values obtained by the analytical function on ADSP-BF533 single-core and ADSP-BF561 dual-core processors are presented. The results were compared, the acceleration coefficient and efficiency coefficients were determined. Acceleration coefficients are plotted on the graphics. For dual-core signal processors, we were able to use the generated parallel algorithm to reduce the time spent processing signals to a single-core. The performance acceleration coefficient increased to 1,557 and the performance coefficient to 0.7783.