The Design Of Broadband I/O Circuits [The Analog Mind]

The transport of high-speed data to and from chips requires input-output (I/O) interfaces with a commensurately wide bandwidth. In addition to the parasitic capacitances that the output driver in a transmitter (TX) and the input stage in a receiver (RX) present to the signal path, both interfaces must also deal with the capacitances associated with electrostatic discharge (ESD) protection devices. The I/O design thus becomes increasingly more challenging as greater speeds are sought. In this article, we design I/O circuits for a data rate of 40 Gb/s with a singleended voltage swing of 0.5 V_pp while focusing on the use of T-coils. The reader is referred to [1]-[5] for background information.